Data Placement & Allocation Schemes (S1–S6)
Which channel, die, and plane should each write go to? It matters more than you'd think.
When the FTL receives a write, it must choose where in the physical hierarchy to put it: which channel, chip, die, and plane. The rule it uses is the allocation (data-placement) scheme. A good scheme maximizes parallelism and spreads wear evenly; a bad one leaves channels idle or hammers a few blocks.
An allocation scheme decides the order in which the four parallel dimensions (channel, chip, die, plane) are cycled as consecutive logical pages arrive. Different orders = different striping = different parallelism and wear behavior.
Striping consecutive pages across channels first keeps every channel busy — maximum throughput.
The six static schemes
The paper studies six placement orders, labeled S1–S6. Each is a different priority order of the four dimensions, e.g.:
| Scheme | Priority order (first dimension varies fastest) |
|---|---|
| S1 | Chip → Die → Plane → Channel |
| S2 | Channel → Chip → Die → Plane |
| S3 | Channel → Plane → Chip → Die |
| S4 | Channel → Die → Chip → Plane |
| S5 | Channel → Plane → Die → Chip |
| S6 | Channel → Die → Plane → Chip |
A subtle but important rule: you need at least 2 chips for all six schemes to be genuinely different. With a single chip, some schemes become mathematically identical (S2≡S4, S3≡S5) — an error that can invalidate a comparison.
Analogy. It's like dealing cards to players around a table. Do you give each player one card before looping back (spread the load), or deal one player their whole hand first (pile it up)? Same cards, very different balance.
In the EyanaSSDSim paper & simulator. This is a core contribution of the paper: comparing S1–S6 on write amplification and wear evenness. That's why the Live Simulator requires Chips ≥ 2 — so the scheme comparison stays valid. The nested grid lets you see the striping directly.