Inside the Chip: Cells, Pages, Blocks, Planes, Dies, Channels
The physical hierarchy of a flash SSD — and why every level exists.
An SSD is built from a strict physical hierarchy. Understanding it is the key to understanding everything else, because operations happen at different levels: you read/write pages, but you erase blocks, and you gain speed through parallel channels.
A page lives in a block, blocks live in a plane, planes in a die, dies in a chip, chips on a channel.
The levels, smallest to largest
- Cell — one transistor holding 1–4 bits (SLC/MLC/TLC/QLC). The atom of storage.
- Page — the smallest unit you can read or write. Typically 4–16 KB.
- Block — the smallest unit you can erase. Hundreds to thousands of pages.
- Plane — a group of blocks that can operate somewhat independently.
- Die (LUN) — one or more planes; the unit that executes a command.
- Chip / package — one or more dies sharing a package.
- Channel — a bus connecting several chips to the controller; channels run in parallel.
Remember the mismatch: the read/write unit is a page, but the erase unit is a whole block. This size mismatch is the root cause of garbage collection and write amplification.
Why so many levels? Parallelism.
Each channel, die, and plane can work at the same time. Spreading writes across them is how an SSD reaches gigabytes per second from chips that are individually slow. How you spread data across these units is called the allocation scheme, and choosing it well is one of the paper's central questions.
Analogy. A supermarket with one cashier is slow no matter how fast they scan. Open 8 lanes (channels) with 4 baggers each (dies/planes) and throughput multiplies. The SSD controller is the manager deciding which lane each customer joins.
In the EyanaSSDSim paper & simulator. On the Live Simulator you choose Channels, Chips, Dies, Planes, Blocks/plane, and Pages/block yourself. The nested grid you see is exactly this hierarchy — each small square is one block, grouped by plane → die → chip → channel.